NEC SX-9
The SX-9 is a supercomputer built by NEC Corporation. The SX-9 Series implements an SMP system in a compact node module and uses an enhanced version of the single chip vector processor that was introduced with the SX-6. The NEC SX-9 processors run at 3.2 GHz, with eight-way replicated vector pipes, each having two multiply units and two addition units; this results in a peak vector performance of 102.4 gigaFLOPS. For non-vectorized code, there is a scalar processor that runs at half the speed of the vector unit, i.e. 1.6 GHz. Up to 16 CPUs and 1 terabyte of memory may be used in a single node. Each node is packaged in an air-cooled cabinet, similar in size to a standard 42U computer rack. The SX-9 series ranges from the single-node SX-9/B system with 4 CPUs to the maximum expansion stage with 512 nodes, 8,192 CPUs, and 970 TFLOPS peak performance. There is up to 4 TB/s shared memory bandwidth per node and 2×128 GB/s node interconnect bandwidth. The operating system is NEC's SUPER-UX, a Unix-like OS.
The SX-9 has the world's fastest vector CPU core.[1][2] A fully equipped system with 512 nodes would be the world's fastest vector supercomputer at the time of release in the first quarter of 2008.
The German national meteorological service (DWD) operated two independent SX-9 clusters, with 976 processors, 31,232 GB of RAM and 98 TFLOPS performance[3] in total.
NEC Published Product Highlights
- 1.6 TFLOPS max. peak performance per node
- 350 million transistors per CPU, 1.0 V, 8,960 pins (1,791 signal pins)[4]
- Up to 16 CPUs per node, manufactured in 65 nm CMOS cu technology, 11 copper layers
- Up to 64 GB of memory per CPU, 1 TB in a single node
- Up to 4 TB/s bandwidth per node, 256 GB/s per CPU
- IXS Super-Switch between nodes, up to 512 nodes supported, 256 GB/s per node (128 GB/s for each direction)
- 50% less power consumption compared to the NEC SX-8R
See also
External links
References
- ↑ http://doi.ieeecomputersociety.org/10.1109/IPDPS.2009.5161089
- ↑ http://insidehpc.com/2008/11/12/nec-sx-9-and-the-hpc-challenge-a-fairy-tale-story/
- ↑ http://www.dwd.de/bvbw/generator/DWDWWW/Content/Presse/Pressekonferenzen/2009/PK__17__03__09/20090317__ZundF__Rechner,templateId=raw,property=publicationFile.pdf/20090317_ZundF_Rechner.pdf
- ↑ LSI and Circuit Technologies of the SX-9 TANAHASHI Toshio, TSUCHIDA Junichi, MATSUZAWA Hajime, NIWA Kenji, SATOH Tatsuo, KATAGIRI Masaru, NEC TECHNICAL JOURNAL, Vol.3, No.4, 2008
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